1. Field of the Invention
The present invention relates to a method of driving a liquid crystal display and a driver circuit for driving the liquid crystal display as well as an electronic device with the driver circuit, and more particularly to an improvement of the driver circuit and the driving method for driving a color liquid crystal display with a relatively small display screen in a line inversion driving system or in a frame inversion driving system at a reduced power consumption.
2. Description of the Related Art
The liquid crystal display has been applied to various electronic devices such as note-type computers, palm-type computers, pocket-type computers, mobile terminals such as personal digital assistants, mobile phones, and personal handy-phone systems. The advanced liquid crystal display is a color liquid crystal display.
FIG. 1 is a block diagram illustrative of a first conventional driver circuit for driving a color liquid crystal display. A color liquid crystal display 1 may be driven by an active matrix driving system using thin film transistors as switching devices. The color liquid crystal display 1 includes a plurality of scanning lines or gate lines which extend parallel to each other in a column direction at a constant pitch, and a plurality of data lines or source lines which extend parallel to each other in a row direction at another constant pitch, as well as a two-dimensional matrix array of pixels, each of which is positioned in an area defined by adjacent two of the scanning lines and adjacent two of the data lines.
Each of the pixels further includes a liquid crystal cell as an equivalent capacitive load, a common electrode, a thin film transistor for driving the liquid crystal cell, and a data electrode for storing data charge in a vertical synchronizing term. A gate electrode of the thin film transistor is connected to the scanning line. The gate electrode of the thin film transistor serves as a scanning electrode.
The color liquid crystal display 1 may be driven as follows. The common electrode is applied with a common potential Vcom. The data electrode is applied with data signals, wherein the data signals may include data red signals, data green signals and data blue signals, which have been generated from red data DR, green data DG, and blue data DB as digital image data. The scanning electrode is applied with a scanning signal which has been generated from a horizontal synchronizing signal SH and a vertical synchronizing signal SV.
The following description with reference to FIG. 1 will be made assuming that the color liquid crystal display 1 is a normally white type color liquid crystal display which is high in transitivity under no voltage application.
The driver circuit for driving the color liquid crystal display 1 mainly includes a control circuit 2, a gray scale power supply 3, a common power supply 4, a data electrode driver circuit 5, and a scanning electrode driver circuit 6.
The control circuit 2 may, for example, comprise an application specific integrated circuit (ASIC). The control circuit 2 receives parallel inputs of red data DR of 6-bits, green data DG of 6-bits and blue data DB of 6-bits. The control circuit 2 converts the red data DR, green data DG and blue data DB into 18-bits display data D00-D05, D10-D15 and D20-D25 respectively, and outputs the 18-bits display data. The 18-bits display data outputted from the control circuit 2 are supplied to the data electrode driver circuit 5.
The control circuit 2 also receives further inputs of a dot-clock signal DCLK, a horizontal synchronizing signal SH, and a vertical synchronizing signal SV, so that the control circuit 2 generates a strobe signal STB, a clock signal CLK, a horizontal start pulse signal STH, a vertical start pulse signal STV, a polarity signal POL, a data inversion signal INV from the dot-clock signal DCLK, the horizontal synchronizing signal SH, and the vertical synchronizing signal SV. The strobe signal STB, the clock signal CLK, the horizontal start pulse signal STH and the data inversion signal INV are supplied to the data electrode driver circuit 5. The polarity signal POL is supplied to the gray scale power supply 3 and the common power supply 4. The vertical start pulse signal STV is supplied to the scanning electrode driver circuit 6.
The strobe signal STB has the same cycle as the horizontal synchronizing signal SH. The clock signal CLK may be either identical with or different in frequency from the dot-clock signal DCLK. The clock signal CLK may be used for allowing shift registers in the data electrode driver circuit 5 to generate sampling pulse signals SP1-SP176 from the horizontal start pulse signal STH.
The horizontal start pulse signal STH is identical in cycle to the horizontal synchronizing signal SH, and delayed from the strobe signal STB by a time corresponding to a few pulses of the clock signal CLK. The polarity signal POL is inverted in a single line unit or in a single horizontal synchronizing cycle for alternating current driving of the color liquid crystal display 1. The vertical start pulse signal STV has the same cycle as the vertical synchronizing signal SV.
The data inversion signal INV is used for the purpose of reducing the power which is consumed by the control circuit 2. If the current 18-bits display data D00-D05, D10-D15 and D20-D25 has at least 10-inverted bits from the previous 18-bits display data, the data inversion signal INV is inverted in synchronizing with the clock signal CLK, instead of inversions of the current 18-bits display data D00-D05, D10-D15 and D20-D25 for the following reasons.
It is general that the control circuit 2 and the gray scale power supply 3 are integrated over a printed board, whilst the data electrode driver circuit 5 is mounted as a tape carrier package (TCP) over a film tape carrier which provides an electrical connection between the printed board and the color liquid crystal display 1. The printed board is mounted at an upper portion on a back face of a back light which is attached to the color liquid crystal display 1.
18-signal lines are provided on the film carrier tape for transmitting the 18-bits display data D00-D05, D10-D15 and D20-D25 from the control circuit 2 to the data electrode driver circuit 5. The 18-signal lines have a line capacitance. In addition, the data electrode driver circuit 5 has an input capacitance of about 20 pF from the control circuit 2. A sufficient current for charging and discharging the line capacitance and the input capacitance would be needed if the polarity of the 18-bits display data D00-D05, D10-D15 and D20-D25 are inverted and supplied to the data electrode driver circuit 5 from the control circuit 2. For reducing the necessary charge and discharge currents to the line capacitance and the input capacitance, it is effective that the data inversion signal INV is inverted, instead of inversions of the 18-bits display data D00-D05, D10-D15 and D20-D25. The reduction of the charge and discharge currents results in a reduction in the power consumed by the control circuit 2.
FIG. 2 is a circuit diagram illustrative of a circuit configuration of a gray scale power supply in the driver circuit shown in FIG. 1. The gray scale power supply 3 includes a series connection of resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, a first pair of switches 8-a and 8-b, a second pair of switches 9-a and 9-b, a single inverter 10, and voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7 11-8, and 11-9 as well as gray scale voltage input ports which receive gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9. The gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 have been set for gamma-control.
The gray scale power supply 3 amplifies the gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 and supplies the amplified gray scale voltages to the data electrode driver circuit 5. The polarity inversions of the gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 between positive and negative potentials with reference to the common voltage Vcom applied to the common electrode are made based on the polarity signal POL in the single line unit.
The resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10 are different in resistance values from each other. The switch 8-a has a first terminal applied with a power voltage VDD and a second terminal connected to a first end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, wherein the resistance 7-1 is connected directly to the second terminal of the switch 8-a. The switch 8-a also has a control terminal applied with the polarity signal POL. If the polarity signal POL is low level “L”, then the switch 8-a is in OFF-state. If the polarity signal POL is high level “H”, then the switch 8-a is in ON-state, whereby the power voltage VDD is applied to the first end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10.
The inverter 10 receives the polarity signal POL and generates an inverted polarity signal /POL. The switch 8-b has a first terminal grounded and a second terminal connected to the first end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, wherein the resistance 7-1 is connected directly to the second terminal of the switch 8-b. The switch 8-b also has a control terminal connected to an output from the inverter 10 for receiving the inverted polarity signal /POL from the inverter 10. If the inverted polarity signal /POL is low level “L”, then the switch 8-b is in OFF-state. If the inverted polarity signal /POL is high level “H”, then the switch 8-b is in ON-state, whereby the ground potential GND is applied to the first end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10.
The switch 9-a has a first terminal grounded and a second terminal connected to a second end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, wherein the resistance 7-10 is connected directly to the second terminal of the switch 9-a. The switch 9-a also has a control terminal applied with the polarity signal POL. If the polarity signal POL is low level “L”, then the switch 9-a is in OFF-state. If the polarity signal POL is high level “H”, then the switch 9-a is in ON-state, whereby the ground potential GND is applied to the second end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10.
The switch 9-b has a first terminal applied with the power voltage VDD and a second terminal connected to the second end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, wherein the resistance 7-10 is connected directly to the second terminal of the switch 9-b. The switch 9-b also has a control terminal connected to the output from the inverter 10 for receiving the inverted polarity signal /POL from the inverter 10. If the inverted polarity signal /POL is low level “L”, then the switch 9-b is in OFF-state. If the inverted polarity signal /POL is high level “H”, then the switch 9-b is in ON-state, whereby the ground potential GND is applied to the second end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10.
The series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10 has first to ninth nodes N1, N2, N3, N4, N5, N6, N7, N8 and N9, at which divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are generated respectively if the first and second ends of the series connection are biased. The first to ninth nodes N1, N2, N3, N4, N5, N6, N7, N8 and N9 are connected to inputs of the voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, 11-8 and 11-9 respectively, whereby the divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are amplified by the voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, 11-8 and 11-9 respectively.
If the polarity signal POL is the high level “H”, then the first end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10 is applied with the power voltage VDD, whilst the second end thereof is applied with the ground voltage, whereby positive polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are generated at the first to ninth nodes N1, N2, N3, N4, N5, N6, N7, N8 and N9 respectively in accordance with respective ratios of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, provided that VDD>V1>V2>V3>V4>V5>V6>V7>V8>V9>GND. The positive polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are then amplified by the voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, 11-8 and 11-9 respectively to generate the first to ninth positive polarity gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 which will subsequently be supplied to the data electrode driver circuit 5, provided that the VI1>VI2>VI3>VI4>VI5>VI6>VI7>VI8>VI9.
If the polarity signal POL is the low level “L”, then the first end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10 is applied with the ground voltage, whilst the second end thereof is applied with the power voltage VDD, whereby negative polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are generated at the first to ninth nodes N1, N2, N3, N4, N5, N6, N7, N8 and N9 respectively in accordance with respective ratios of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, provided that VDD<V1<V2<V3<V4<V5<V6<V7<V8<V9<GND. The negative polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are then amplified by the voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, 11-8 and 11-9 respectively to generate the first to ninth negative polarity gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 which will subsequently be supplied to the data electrode driver circuit 5, provided that VI1<VI2 <VI3<VI4<VI5<VI6<VI7<VI8<VI9.
The common power supply 4 receives an input of the polarity signal “POL” from the control circuit 2 and supplies the common potential Vcom to the common electrode of the color liquid crystal display 1. If the polarity signal “POL” is in the high level “H”, then the common power supply 4 sets the common potential Vcom at the ground level GND. If the polarity signal “POL” is in the low level “L”, then the common power supply 4 sets the common potential Vcom at the power voltage level VDD.
The data electrode driver circuit 5 receives the strobe signal STB, the clock signal CLK, the horizontal start pulse signal STH and the data inversion signal INV in addition to the 18-bits display data D00-D05, D10-D15 and D20-D25 from the control circuit 2. The data electrode driver circuit 5 selects the gray scale voltages based on the 18-bits display data D00-D05, D10-D15 and D20-D25 under the controls by the strobe signal STB, the clock signal CLK, the horizontal start pulse signal STH and the data inversion signal INV. The data electrode driver circuit 5 applies the selected gray scale voltages to the data electrodes of the color liquid crystal display 1.
The scanning electrode driver circuit 6 receives the vertical start pulse signal STV from the control circuit 2, so that the scanning electrode driver circuit 6 generates, in sequence, the scanning signals and applies the scanning signals to the scanning electrodes of the color liquid crystal display 1.
FIG. 3 is a block diagram illustrative of the data electrode driver circuit shown in FIG. 1. It is assumed that a resolution of the color liquid crystal display 1 is defined by 176×220 pixels. Since each pixel comprises three-dots of red (R), green (G) and blue (B), then the color liquid crystal display 1 has a 528×220 dot-pixels.
The data electrode driver circuit 5 includes a shift register 12, a data buffer 13, a data register 14, a control circuit 15, a data latch 16, a gray scale voltage generating circuit 17, a gray scale voltage selecting circuit 18, and an output circuit 19.
The shift register 12 is a serial-in parallel-out shift register which comprises 176 delay-flip-flops. The shift register 12 receives the clock signal CLK and the horizontal start pulse signal STH from the control circuit 2, so that the shift register 12 shifts the horizontal start pulse signal STH in synchronizing with the clock signal CLK, and generates sampling pulses SP1, SP2, - - - SP176 which comprise a 176-bits parallel-out signal.
The data buffer 13 receives the 18-bits display data D00-D05, D10-D15 and D20-D25 and the data inversion signal INV from the control circuit 2, so that the data buffer 13 performs an inversion operation of the 18-bits display data in accordance with the data inversion signal INV, so that the data buffer 13 outputs 18-bits display data D′00-D′05, D′10-D′15 and D′20-D′25.
FIG. 4 is a partial circuit diagram illustrative of a part of the circuit configuration of the data buffer shown in FIG. 3. The data buffer 13 comprises first to eighteenth data buffer circuits 13a1, 13a2, 13a3, - - - 13a18, and a single control unit 13b. The control unit 13b includes two series connections of plural inverters. The two series connections of plural inverters in the control unit 13b receive the data inversion signal INV and the clock signal CLK from the control circuit 2 respectively, so that the control unit 13b delays the data inversion signal INV and the clock signal CLK from the control circuit 2 by predetermined delay times respectively, whereby the control unit 13b supplies a delayed clock signal CLK1 and a delayed data inversion signal INV1 to the first data buffer circuit 13a1.
The control unit 13b also supplies other delayed clock signals CLK2, CLK3, - - - CLK18 and other delayed data inversion signals INV2, INV3 - - - INV18 to the remaining second to eighteenth data buffer circuits 13a2, 13a3, - - - 13a18, respectively. The first to eighteenth data buffer circuits 13a1, 13a2, 13a3, - - - 13a18 have the same circuit configuration and perform the same operations, for which reason the following description will focus on the first data buffer circuit 13a1 only.
The first data buffer circuit 13a1 includes a D-flip-flop 20-1, inverters 21-1, 22-1 and 23-1, and a switching circuit 24-1. The switching circuit 24-1 comprises two parallel switches 24-1a and 24-1b. The control unit 13b supplies the delayed clock signal CLK1 to the D-flip-flop 20-1 and the delayed data inversion signal INV1 to the switching circuit 24-1.
The D-flip-flop 20-1 latches a single bit display data D00 in synchronizing with the clock signal CLK1 for a term corresponding to the single pulse width of the clock signal CLK1, and outputs the single bit display data D00. The inverter 21-1 inverts the single bit display data D00, so that the inverted bit display data D00 is supplied to the switch 24-1b. The non-inverted bit display data D00 outputted from the D-flip-flop 20-1 is also directly supplied to the switch 24-1a. 
If the delayed data inversion signal INV1 from the control unit 13b is high level “H”, then the switching circuit 24-1a is placed in the ON-state, whilst the switching circuit 24-1b is placed in the OFF-state, whereby the non-inverted bit display data D00 is transmitted through the series connection of the inverters 22-1 and 23-1 to an output terminal as the output bit display data D′00.
If the delayed data inversion signal INV1 from the control unit 13b is low level “L”, then the switching circuit 24-1a is placed in the OFF-state, whilst the switching circuit 24-1b is placed in the ON-state, whereby the inverted bit display data D00 is transmitted through the series connection of the inverters 22-1 and 23-1 to the output terminal as the output single bit display data D′00.
With reference again to FIG. 3, the data register 14 receives the 18-bits display data D′00-D′05, D′10-D′5 and D′20-D′25 from the data buffer 13 and also receives the sampling pulses SP1, SP2, - - - SP176 from the shift register 12. In synchronizing with the sampling pulses SP1, SP2, - - - SP176, the data register 14 accepts the inputs of the 18-bits display data D′00-D′05, D′10-D′15 and D′20-D′25 and transmits display data PD1, PD2, PD3, - - - PD528 to the data latch 16.
The control circuit 15 comprises a series connection of plural inverters. The control circuit 15 receives the strobe signal STB from the control circuit 2, so that the control circuit 15 generates a delayed strobe signal STB1 which has a predetermined delay time from the strobe signal STB as well as generates a switch control signal SWA which is opposite in phase to the delayed strobe signal STB1. The control circuit 15 transmits the delayed strobe signal STB1 to the data latch 16 and also transmits the switch control signal SWA to the output circuit 19.
The data latch 16 accepts the inputs of the display data PD1, PD2, PD3, - - - PD528 in synchronizing with a rising edge of the delayed strobe signal STB1 and holds the display data PD1, PD2, PD3, - - - PD528 for a time period of the vertical synchronizing term. In synchronizing with the next rising edge of the delayed strobe signal STB1, the data latch 16 transmits the display data PD1, PD2, PD3, - - - PD528 to the gray scale voltage selecting circuit 18.
FIG. 5 is a circuit diagram illustrative of the gray scale voltage generating circuit shown in FIG. 3. The gray scale voltage generating circuit 17 comprises a single series connection of first to sixty third resistances 25-1, 25-2, 25-3, 25-4, - - - 25-63. The first to sixty third resistances 25-1, 25-2, 25-3, 25-4, - - - 25-63 have respective resistance values which are adjusted to applied voltage-to-transitivity characteristic of the color liquid crystal display 1. The gray scale voltage generating circuit 17 receives first to ninth gray scale voltages VI1, VI2, VI3, - - - VI9 from the gray scale power supply 3.
The first gray scale voltage VI1 is supplied to a first node of the first side of the first resistance 25-1. The second gray scale voltage VI2 is supplied to an eighth node between the seventh resistance 25-7 and the eighth resistance 25-8. The third gray scale voltage VI3 is supplied to a sixteenth node between the fifteenth resistance 25-15 and the sixteenth resistance 25-16. The fourth gray scale voltage VI4 is supplied to a twenty fourth node between the twenty third resistance 25-23 and the twenty fourth resistance 25-24. The fifth gray scale voltage VI5 is supplied to a thirty second node between the thirty first resistance 25-31 and the thirty second resistance 25-32. The sixth gray scale voltage VI6 is supplied to a fortieth node between the thirty ninth resistance 25-39 and the fortieth resistance 25-40. The seventh gray scale voltage VI7 is supplied to a forty eighth node between the forty seventh resistance 25-47 and the forty eighth resistance 25-48. The eighth gray scale voltage VI8 is supplied to a fifty sixth node between the fifty fifth resistance 25-55 and the fifty sixth resistance 25-56. The ninth gray scale voltage VI9 is supplied to a sixty fourth node of a second side of the sixty third resistance 25-63.
The gray scale voltage generating circuit 17 generates first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 at the first to sixty fourth nodes respectively, wherein the generated first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 depend on the first to ninth gray scale voltages VI1, VI2, VI3, - - - VI9 from the gray scale power supply 3 and also on the respective resistance values of the first to sixty third resistances 25-1, 25-2, 25-3, - - - 25-63. Each of the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 may individually be inverted between positive polarity and negative polarity with reference to the common potential Vcom.
With reference back to FIG. 3, the generated first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 are supplied to the gray scale voltage selecting circuit 18. Namely, a gray scale signal of 64 bits is supplied from the gray scale voltage generating circuit 17 to the gray scale voltage selecting circuit 18.
The gray scale voltage selecting circuit 18 comprise first to five hundred twenty eighth gray scale voltage selecting units 18-1, 18-2, 18-3, - - - , 18-528. Each of the first to five hundred twenty eighth gray scale voltage selecting units 18-1, 18-2, 18-3, - - - , 18-528 receives corresponding one of 6-bits display data PD1, PD2, - - - PD528, so as to select one of the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 based on the corresponding one of 6-bits display data PD1, PD2, - - - PD528, whereby the selected one gray scale voltage is supplied to the output circuit 19. For example, the first gray scale voltage selecting unit 18-1 receives the 6-bits display data PD1 to select one of the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 based on the 6-bits display data PD1, whereby the selected one gray scale voltage is supplied to the output circuit 19.
The first to five hundred twenty eighth gray scale voltage selecting units 18 -, 18-2, 18-3, - - - , 18-528 have the same circuit configuration, for which reason the following description will focus only on the first gray scale voltage selecting unit 18-1. The output circuit 19 comprises first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - , 19-528 which are connected to the first to five hundred twenty eighth gray scale voltage selecting units 18-1, 18-2, 18-3, - - - , 18-528 respectively. The first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - , 19-528 have the same circuit configuration, for which reason the following description will focus only on the first output unit 19-1.
FIG. 6 is a circuit diagram illustrative of the first gray scale voltage selecting unit included in the gray scale voltage selecting circuit and a first output unit included in the output circuit of FIG. 3. The first gray scale voltage selecting unit 18-1 comprises a single multiplexer 26, first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64, and first to sixty fourth inverters 28-1, 28-2, 28-3, - - - 28-64. Each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 comprises a pair of p-channel MOS field effect transistor 29a and an n-channel MOS field effect transistor 29b. 
A gate of the p-channel MOS field effect transistor 29a of each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 receives the display data PD1 from the multiplexer 26. A gate of the n-channel MOS field effect transistor 29b of each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 receives inverted display data /PD1 through the corresponding one of the first to sixty fourth inverters 28-1, 28-2, 28-3, - - - 28-64 from the multiplexer 26.
The first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 also receive the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 from the gray scale voltage generating circuit 17 respectively. For example, the first transfer gate 27-1 receives the first gray scale voltage V1. The single multiplexer 26 receives the 6-bits display data PD1 from the data latch 16 for selecting one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 based on the received 6-bits display data PD1, whereby the selected one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 turns ON, and the selected one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 outputs the corresponding one of the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 as a data red signal, a data green signal or a data blue signal.
The first output unit 19-1 is connected to the first gray scale voltage selecting unit 18-1. The first output unit 19-1 comprises a first amplifier 30-1, and a first switch 31-1. The first amplifier 30-1 receives the data red signal, a data green signal or a data blue signal as the gray scale voltage from the first gray scale voltage selecting unit 18-1 for amplifying the received signal. Each of the first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - 19-528 also receives a switch control signal SWA from the control circuit 15. The first to five hundred twenty eighth switches 31-1, 31-2, 31-3, - - - 31-528 of the first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - 19-528 receive the switch control signal SWA from the control circuit 15.
If the first switch 31-1 of the first output unit 19-1 turns ON based on the switch control signal SWA from the control circuit 15, then the amplified data red, green or blue signal S1 is outputted from the first output unit 19-1. As shown in FIG. 3, the output circuit 19 outputs the first to five hundred twenty eighth data red, green and blue signals S1, S2, S3, - - - S528 which are then supplied to the data electrodes of the color liquid crystal display 1.
FIG. 7 is a timing chart illustrative of operations of the control circuit, the gray scale power supply 3, the common power supply 4 and the data electrode driver circuit 5 in FIG. 1. The control circuit 2 supplies the data electrode driver circuit 5 with the strobe signal STB, the clock signal CLK, the horizontal start pulse signal STH delayed by a few clock pulses of the clock signal CLK from the strobe signal STH, and the polarity signal POL. The shift register 12 in the data electrode driver circuit 5 shifts the horizontal start pulse signal STH and outputs the sampling pulse signals SP1-SP176 of 176 bits in synchronizing with the clock signal CLK.
The control circuit 2 also converts the red data DR, green data DG, and blue data DB, into the 18-bits display data D00-D05, D10-D15 and D20-D25 which are then supplied to the data electrode driver circuit 5. The data buffer 13 in the data electrode driver circuit 5 receives the 18-bits display data D00-D05, D10-D15 and D20-D25 from the control circuit 2 and holds the 18-bits display data D00-D05, D10-D15 and D20-D25 for a time period corresponding a single pulse width of the clock signal CLK in synchronizing with the clock signal CLK, before the data buffer 13 supplies the data register 14 with the 18-bits display data D′00-D′05, D′10-D′15 and D′20-D′25.
The data register 14 in the data electrode driver circuit 5 accepts serious inputs of the 18-bits display data D′00-D′05, D′10-D′15 and D′20-D′25 as the 6-bits display data PD1, PD2, - - - PD528 in synchronizing with the sampling pulse signals SP1-SP176. The data latch 16 accepts simultaneous inputs of the 6-bits display data PD1, PD2, - - - PD528 in synchronizing with a rising edge of the strobe signal STB and latches the 6-bits display data PD1, PD2, - - - PD528 for a single horizontal time period.
The gray scale power supply 3 shown in FIG. 2 receives the polarity signal POL. If the polarity signal POL is high level “H”, then the switches 8a and 9a turn ON as well as the switches 8b and 9b turn OFF, whereby the first side of the first resistance 7-1 is applied with the power voltage VDD whilst the second side of the tenth resistance 7-10 is applied with the ground voltage GND, so that the series connection of the first to tenth resistances 7-1, 7-2, 7-3, - - - 7-10 is biased between the power voltage VDD and the ground voltage GND. As a result, positive polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are generated at the first to ninth nodes N1, N2, N3, N4, N5, N6, N7, N8 and N9 respectively in accordance with respective ratios of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, provided that VDD>V1>V2>V3 >V4>V5>V6>V7>V8>V9>GND. The positive polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are then amplified by the voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, 11-8 and 11-9 respectively to generate the first to ninth positive polarity gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 which will subsequently be supplied to the gray scale voltage generating circuit 17 in the data electrode driver circuit 5, provided that the VI1>VI2>VI3>VI4>VI5>VI6>VI7>VI8>VI9.
The gray scale voltage generating circuit 17 generates first to sixty fourth positive polarity gray scale voltages V1, V2, V3, - - - V64 at the first to sixty fourth nodes respectively, wherein the generated first to sixty fourth positive polarity gray scale voltages V1, V2, V3, - - - V64 depend on the first to ninth gray scale voltages VI1, VI2, VI3, - - - VI9, wherein V1>V2>V3> - - - >V64, The first to sixty fourth positive polarity gray scale voltages V1, V2, V3, - - - V64 are then supplied to the gray scale voltage selecting circuit 18 in the data electrode driver circuit 5.
Each of the first to five hundred twenty eighth gray scale voltage selecting units 18-1, 18-2, 18-3, - - - , 18-528 receives corresponding one of 6-bits display data PD1, PD2, - - - PD528.
A gate of the p-channel MOS field effect transistor 29a of each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 receives the display data PD from the multiplexer 26. A gate of the n-channel MOS field effect transistor 29b of each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 receives inverted display data /PD through the corresponding one of the first to sixty fourth inverters 28-1, 28-2, 28-3, - - - 28-64 from the multiplexer 26. The first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 also receive the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 from the gray scale voltage generating circuit 17 respectively. The single multiplexer 26 receives the 6-bits display data PD1 from the data latch 16 for selecting one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 based on the received 6-bits display data PD1, whereby the selected one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 turns ON, and the selected one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 outputs the corresponding one of the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 as a data red signal, a data green signal or a data blue signal.
The first amplifier 30-1 receives the data red signal, a data green signal or a data blue signal as the gray scale voltage from the first gray scale voltage selecting unit 18-1 for amplifying the received signal. Each of the first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - 19-528 also receives a switch control signal SWA from the control circuit 15. The first to five hundred twenty eighth switches 31-1, 31-2, 31-3, - - - 31-528 of the first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - 19-528 receive the switch control signal SWA from the control circuit 15, wherein the switch control signal SWA rises at the timing of falling edge of the strobe signal STB. The output circuit 19 outputs the first to five hundred twenty eighth data red, green and blue signals S1, S2, S3, - - - S528 which are then supplied to the data electrodes of the color liquid crystal display 1.
In FIG. 7, shown is the signal S1 which is the data red signal, in case that the display data PD1 is “000000”. In this case, the transfer gate 27-1 in the first gray scale voltage selecting unit 18-1 turns ON based on the display data PD1 “000000”, whereby the positive polarity gray scale voltage V1 is outputted as the data red signal S1. The data red signal S1 is represented by a broken line when the strobe signal “STB” is high level because the switch 31-1 is in the OFF and the signal S1 applied to the data electrode of the color liquid crystal display 1 is in the high impedance state.
The common power supply 4 supplies the ground level GND to the common electrode of the color liquid crystal display 1 based on the polarity signal POL of high level “H”, wherein the common potential of the common electrode of the color liquid crystal display 1 becomes the ground level GND. The pixel corresponding to the data electrode shows black, assuming that the color liquid crystal display 1 is of the normally white type.
If the polarity signal POL is low level “L”, then the switches 8a and 9a turn OFF as well as the switches 8b and 9b turn ON, whereby the first side of the first resistance 7-1 is applied with the ground voltage GND whilst the second side of the tenth resistance 7-10 is applied with the power voltage VDD, so that the series connection of the first to tenth resistances 7-1, 7-2, 7-3, - - - 7-10 is biased between the power voltage VDD and the ground voltage GND. As a result, negative polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are generated at the first to ninth nodes N1, N2, N3, N4, N5, N6, N7, N8 and N9 respectively in accordance with respective ratios of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, provided that VDD<V1<V2<V3<V4<V5<V6<V7<V8<V9<GND. The negative polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are then amplified by the voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, 11-8 and 11-9 respectively to generate the first to ninth negative polarity gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 which will subsequently be supplied to the gray scale voltage generating circuit 17 in the data electrode driver circuit 5, provided that VI1<VI2<VI3<VI4<VI5<VI6<VI7<VI8<VI9.
The gray scale voltage generating circuit 17 generates first to sixty fourth negative polarity gray scale voltages V1, V2, V3, - - - V64 at the first to sixty fourth nodes respectively, wherein the generated first to sixty fourth negative polarity gray scale voltages V1, V2, V3, - - - V64 depend on the first to ninth gray scale voltages VI1, VI2, VI3, - - - VI9, wherein V1<V2<V3< - - - <V64. The first to sixty fourth negative polarity gray scale voltages V1, V2, V3, - - - V64 are then supplied to the gray scale voltage selecting circuit 18 in the data electrode driver circuit 5.
Each of the first to five hundred twenty eighth gray scale voltage selecting units 18-1, 18-2, 18-3, - - - , 18-528 receives corresponding one of 6-bits display data PD1, PD2, - - - PD528.
A gate of the p-channel MOS field effect transistor 29a of each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 receives the display data PD from the multiplexer 26. A gate of the n-channel MOS field effect transistor 29b of each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 receives inverted display data /PD through the corresponding one of the first to sixty fourth inverters 28-1, 28-2, 28-3, - - - 28-64 from the multiplexer 26. The first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 also receive the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 from the gray scale voltage generating circuit 17 respectively. The single multiplexer 26 receives the 6-bits display data PD1 from the data latch 16 for selecting one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 based on the received 6-bits display data PD1, whereby the selected one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 turns ON, and the selected one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 outputs the corresponding one of the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 as a data red signal, a data green signal or a data blue signal.
The first amplifier 30-1 receives the data red signal, a data green signal or a data blue signal as the gray scale voltage from the first gray scale voltage selecting unit 18-1 for amplifying the received signal. Bach of the first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - 19-528 also receives a switch control signal SWA from the control circuit 15. The first to five hundred twenty eighth switches 31-1, 31-2, 31-3, - - - 31-528 of the first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - 19-528 receive the switch control signal SWA from the control circuit 15, wherein the switch control signal SWA rises at the timing of falling edge of the strobe signal STB. The output circuit 19 outputs the first to five hundred twenty eighth data red, green and blue signals S1, S2, S3, - - - S528 which are then supplied to the data electrodes of the color liquid crystal display 1.
In FIG. 7, shown is the signal S1 which is the data red signal, in case that the display data PD1 is “000000”. In this case, the transfer gate 27-1 in the first gray scale voltage selecting unit 18-1 turns ON based on the display data PD1 “000000”, whereby the positive polarity gray scale voltage V1 is outputted as the data red signal S1. The data red signal S1 is represented by a broken line when the strobe signal “STB” is high level because the switch 31-1 is in the OFF and the signal S1 applied to the data electrode of the color liquid crystal display 1 is in the high impedance state.
The common power supply 4 supplies the power voltage level VDD to the common electrode of the color liquid crystal display 1 based on the polarity signal POL of low level “L”, wherein the common potential of the common electrode of the color liquid crystal display 1 becomes the power voltage level VDD. The pixel corresponding to the data electrode shows black, assuming that the color liquid crystal display 1 is of the normally white type.
The above-described driving system is so called to as a line-inversion driving system, wherein the data signals applied to the data electrodes are opposite to each other in polarity with reference to corresponding common potentials Vcom between adjacent two of the data lines, provided that the common potentials Vcom are respectively inverted between ground and power voltage levels for every data lines.
The line-inversion driving system has been utilized for the following two reasons. The first reason is that the applications of the same or uniform polarity voltages to the liquid crystal cells shorten the life-time of the color liquid crystal display. The second reason is that the transitivity of the liquid crystal cells is almost independent from the polarity of the applied voltage to the liquid crystal display.
The above described line-inversion driving system, however, has the following disadvantages particularly in case of the mobile phones and personal handy-phone systems. In a stand-by mode, the power ON-state is maintained without, however, any operations by the users, and a predetermined stand-by display is displayed in full-colors on the color liquid crystal display screen, even the users are unlikely to view the display screen. The driver circuit of the color liquid crystal display is driven in the same manner as in the normal mode. This means that, in the stand-by mode, the driver circuit consumes the same power as in the normal mode. It is desirable to suppress the power consumption by the driver circuit in the stand-by mode as many as possible.
FIG. 8 is a view illustrative of a display screen of the mobile phone or the personal handy-phone system. A display screen 1 of the mobile phone or the personal handy-phone system includes a top display region 32, a center display region 33 and a bottom display region 34. The top display region 32 displays a battery mark 32a and an antenna mark 32b. The battery mark 32a indicates a charge-level of a battery accommodated in the mobile phone or the personal handy-phone system. The antenna mark 32b indicates whether the position of the mobile phone or the personal handy-phone system is in a service area of a wireless phone service on a mobile communication network.
The center display region 33 displays images of the contents attached to e-mails and provided from Word Wide Web servers. The bottom display region 34 displays month-and-day information 34a and clock-time information 34b. The center display region 33 shows the full color display. The top and bottom display regions 32 and 34 show monochrome or 8-colors displays.
For performing the monochrome or 8-colors display on the top and bottom display regions 32 and 34, the conventional driver circuit of the color liquid crystal display 1 operates the data electrode driver circuit 5 in the same manners as performing the full-color display on the center display region 33. This causes unnecessary power consumption by the conventional driver circuit. It is thus desirable to suppress the power consumption for displaying the top and bottom display regions 32 and 34.
Another driving system, for example, the frame inversion system also has the same disadvantages as described above. In the frame inversion system, the data signals applied to the data electrodes are opposite to each other in polarity with reference to corresponding common potentials Vcom between adjacent two frames, provided that the common potentials Vcom are respectively inverted between ground and power voltage levels for every frames.
The above described disadvantages of the line-inversion driving system and the frame-inversion driving system are also common to other portable or mobile electric devices than the mobile phones and the personal handy-phone systems, for example, various electronic devices such as note-type computers, palm-type computers, pocket-type computers, mobile terminals such as personal digital assistants.
In the above circumstances, the developments of a novel method of driving a liquid crystal display and of a driver circuit for driving the liquid crystal display as well as of an electronic device with the driver circuit are desirable.